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19-2648; Rev 0; 10/02
KIT ATION EVALU BLE AVAILA
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver
General Description Features
o Guaranteed 400mV Differential Output at 1.5GHz o Selectable Single-Ended or Differential Input o 130ps (max) Part-to-Part Skew at +25C o 20ps Output-to-Output Skew o 365ps Propagation Delay o Synchronous Output Enable/Disable o On-Chip Reference for Single-Ended Inputs o Input Biased to Low when Open o Pin Compatible with MC100EL14
MAX9316A
The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential and one single ended. The selected input is reproduced at five differential outputs. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9316A features low output-to-output skew (20ps), making it ideal for clock and data distribution across a backplane or board. For interfacing to differential HSTL and (LV)PECL signals, this device operates over a 3.0V to 5.5V supply range, allowing high-performance clock or data distribution in systems with a nominal 3.3V or 5.0V supply. For differential (LV)ECL operation, this device operates with a -3.0V to -5.5V supply. The MAX9316A is offered in a 20-pin wide SO package.
Applications
Precision Clock Distribution Low-Jitter Data Repeaters Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM Backplane Base Stations ATE
PART MAX9316AEWP
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 20 Wide SO
Pin Configuration
TOP VIEW
MAX9316A
QO 1 Q0 2 Q1 3 Q D 20 VCC 19 EN 18 VCC 17 N.C. 16 SCLK 15 CLK 14 CLK 13 VBB 12 SEL 11 VEE WIDE SO
Typical Application Circuit
MAX9316A
ZO = 50 Q_
RECEIVER
Q1 4 Q2 5 Q2 6 Q3 7
ZO = 50 Q_
Q3 8 Q4 9
50 50
Q4 10
VTT = VCC - 2.0V
Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
ABSOLUTE MAXIMUM RATINGS
VCC - VEE...............................................................................6.0V Single-Ended Inputs (SCLK, SEL, EN, CLK, CLK) For VCC - VEE 4.2V.........................VEE - 0.3V to VCC + 0.3V For VCC - VEE > 4.2V ........................VEE - 4.2V to VCC + 0.3V CLK to CLK ........................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 20-Pin Wide SO (derate 10mW/C above +70C) ......800mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin Wide SO... ...................................................+100C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC Board 20-Pin Wide SO... .....................................................+58C/W Junction-to-Case Thermal Resistance 20-Pin Wide SO.... .....................................................+20C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (Inputs and Outputs) .........................2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN VCC 1.095 (VCC - VEE) 4.2 Input Low Voltage VIL (VCC - VEE) > 4.2V Input Current Single-Ended Input High Voltage IIN VIL(MIN), VIH(MAX) CLK connected to VBB, Figure 1 CLK connected to VBB, Figure 1 (VCC - VEE) 4.2V CLK connected to VBB, Figure 1 (VCC - VEE) > 4.2V VEE VCC 4.2 -300 VCC 1.095 VEE TYP MAX MIN VCC 1.125 VEE VCC 4.2 -300 VCC 1.125 VEE +25C TYP MAX MIN VCC 1.125 VEE VCC 4.2 -300 VCC 1.125 VEE +85C TYP MAX UNITS
SINGLE-ENDED INPUTS (SCLK, SEL, EN) Input High Voltage VIH VCC VCC 1.495 VCC 1.495 +300 VCC VCC 1.495 VCC 1.495 +300 VCC VCC 1.575 VCC 1.575 +300 A V
V
DIFFERENTIAL INPUTS (CLK, CLK) VIH VCC VCC 1.495 VCC 1.495 VCC VCC 0.095 VCC VCC 1.495 VCC 1.495 VCC VCC 0.095 VCC VCC 1.575 V VCC 4.2 VEE + 1.2 VEE VCC 4.2 VEE + 1.2 VEE VCC 4.2 VEE + 1.2 VEE VCC 1.575 VCC VCC 0.095 V V V
Single-Ended Input Low Voltage
VIL
High Voltage of Differential Input Low Voltage of Differential Input
VIHD VILD
2
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1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 3.0V to 5.5V, outputs loaded with 50 1% to VCC - 2V, SEL = high or low, EN = low, unless otherwise noted. Typical values are at VCC - VEE = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Notes 1, 2, 3)
PARAMETER Differential Input Voltage Input Current OUTPUTS (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage REFERENCE (VBB) Reference Voltage Output (Note 4) POWER SUPPLY Supply Current (Note 5) IEE 30 40 32 40 34 43 mA VBB IBB = 0.5mA VCC 1.40 VCC - VCC 1.19 1.40 VCC - VCC 1.22 1.48 VCC 1.22 V VOH Figure 1 VCC 1.085 VCC - VCC 0.865 1.025 VCC - VCC 0.865 1.025 VCC 0.865 V SYMBOL VIHD VILD IIN VIH, VIL, VIHD, VILD CONDITIONS -40C MIN 0.095 -300 TYP MAX 3.0 +300 MIN 0.095 -300 +25C TYP MAX 3.0 +300 MIN 0.095 -300 +85C TYP MAX 3.0 +300 UNITS V A
MAX9316A
VOL VOH VOL
Figure 1
VCC 1.910 550
VCC - VCC 1.555 1.840 910 550
VCC - VCC 1.620 1.810 910 550
VCC 1.620 910
V
Figure 1
mV
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3
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 3.0V to 5.5V, outputs are loaded with 50 1% to VCC - 2V, input frequency 1.5GHz, input transition time = 125ps (20% to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3V, unless otherwise noted. Typical values are at VCC - VEE = 5.0V.) (Notes 1, 6)
PARAMETER CLK to Q_ Delay (Differential) SCLK to Q_ Delay Output-to-Output Skew (Note 7) Part-to-Part Skew (Note 8) Added Random Jitter (Note 9) Added Deterministic Jitter (Note 9) Switching Frequency Output Rise/Fall Time (20% to 80%) SYMBOL tPLHD1, tPHLD1 tPLHD3, tPHLD3 tSKOO tSKPP tRJ fIN = 1.5GHz clock 1.5Gbps 2E23 - 1 PRBS pattern (VOH - VOL) 400mV, Figure 2 Figure 2 0.8 CONDITIONS Figure 2 VIL = VCC - 1.55V, VIH = VCC - 1.09V, Figure 3 -40C MIN 290 TYP MAX 400 MIN 310 +25C TYP MAX 440 MIN 300 +85C TYP MAX 520 UNITS ps
290
400
310
440
300
520
ps
5
30 110 1.2
20
40 130
20
50 220
ps ps ps (RMS)
0.8
1.2
0.8
1.2
tDJ
50
70
50
70
50
70
PsP-P
fMAX
1.5
1.5
1.5
GHz
tR , t F
80
120
90
130
90
145
ps
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
Measurements are made with the device in thermal equilibrium. Current into a pin is defined as positive. Current out of a pin is defined as negative. DC parameters are production tested at TA = +25C and guaranteed by design over the full operating temperature range. Use VBB only for inputs that are on the same device as the VBB reference. All pins are open except VCC and VEE. Guaranteed by design and characterization. Limits are set at 6 sigma. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Device jitter added to a jitter-free input signal.
4
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1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
Typical Operating Characteristics
(VCC = 5.0V, VIHD = VCC - 1V, VILD = VCC - 1.15V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs loaded with 50 to (VCC - 2V), TA = +25C, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY
MAX9316A toc01
SUPPLY CURRENT vs.TEMPERATURE
40 ALL PINS ARE OPEN EXCEPT VCC AND VEE 36 SUPPLY CURRENT (mA) 900 DIFFERENTIAL OUTPUT VOLTAGE (mV) 800 700 600 500 400 300 200 100 0 -40 -15 10 35 60 85 0
32
28
24
20 TEMPERATURE (C)
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
TRANSITION TIME vs. TEMPERATURE
MAX9316A toc03
PROPAGATION DELAY vs. TEMPERATURE
SCLK MEASUREMENT AT VIH = 2.12V, VCC = +1.82V DIFFERENTIAL CLK
MAX9316A toc05
140 130 TRANSITION TIME (ps) 120 tR 110 100 90 80 -40 -15 10 35 60 tF
420
PROPAGATION DELAY (ps)
400
380
360
340
320 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
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MAX9316A toc02
5
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 VEE SEL FUNCTION Noninverting Q0 Output. Typically terminate with 50 resistor to (VCC - 2V). Inverting Q0 Output. Typically terminate with 50 resistor to (VCC - 2V). Noninverting Q1 Output. Typically terminate with 50 resistor to (VCC - 2V). Inverting Q1 Output. Typically terminate with 50 resistor to (VCC - 2V). Noninverting Q2 Output. Typically terminate with 50 resistor to (VCC - 2V). Inverting Q2 Output. Typically terminate with 50 resistor to (VCC - 2V). Noninverting Q3 Output. Typically terminate with 50 resistor to (VCC - 2V). Inverting Q3 Output. Typically terminate with 50 resistor to (VCC - 2V). Noninverting Q4 Output. Typically terminate with 50 resistor to (VCC - 2V). Inverting Q4 Output. Typically terminate with 50 resistor to (VCC - 2V). Negative Supply Voltage Clock Select Input (Single Ended). Drive low to select the CLK, CLK input. Drive high to select the SCLK input. The SEL threshold is equal to VBB. Internal 30k pulldown to VEE and 30k pullup to VCC. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise, leave it unconnected. Inverting Differential Clock Input. Internal 45k pullup to VCC and 45k pulldown to VEE. Noninverting Differential Clock Input. Internal 30k pulldown to VEE and 45k pullup to VCC. Single-Ended Clock Input. Internal 30k pulldown to VEE and 45k pullup to VCC. Not Internally Connected. Solder to PC board for package thermal dissipation. Positive Supply Voltage. Bypass VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Output Enable Input. Outputs are synchronously enabled on the falling edge of the clock input when EN is low. Outputs are synchronously set to low on the falling edge of the clock input when EN is high. Internal 30k pulldown to VEE and 30k pullup to VCC.
13 14 15 16 17 18, 20
VBB CLK CLK SCLK N.C. VCC EN
19
Detailed Description
The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock or data distribution. A 2-to-1 MUX selects one of the two clock inputs, CLK, CLK and SCLK. The CLK and CLK inputs are differential while the SCLK is single ended. The MUX is switched by the single-ended SEL input. A logic low selects the CLK input and a logic high selects the SCLK input. The SEL logic threshold is set by the internal voltage reference VBB. SEL input can be driven by VCC and VEE or by a singleended (LV)PECL/(LV)ECL signal. The selected input is reproduced at five differential outputs, Q0 to Q4.
Synchronous Enable
The MAX9316A is synchronously enabled and disabled with outputs in the low state to eliminate shortened clock pulses. EN is connected to the input of an edgetriggered D flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are disabled to a low state on the falling edge of the selected clock input after EN goes high. The threshold for EN is equal to VBB.
Power Supply
For interfacing to differential HSTL and (LV)PECL signals, the V CC range is from 3.0 to 5.5V (with V EE
6
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1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver
grounded), allowing high-performance clock or data distribution in systems with a nominal 5.0V supply. For interfacing to differential (LV)ECL, the V EE range is -3.0V to -5.5V (with VCC grounded). Output levels are referenced to VCC and are considered (LV)PECL or (LV)ECL, depending on the level of the V CC supply. With VCC connected to a positive supply and VEE connected to ground, the outputs are (LV)PECL. The outputs are (LV)ECL when VCC is connected to ground and VEE is connected to a negative supply.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency, surface-mount, ceramic, 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC (if the VBB reference is not used, it can be left open).
MAX9316A
Input Bias Resistors
When the CLK and CLK inputs are open, the internal bias resistors set the inputs to differential low state. The inverting input (CLK) is biased with a 45k pullup to VCC and a 45k pulldown to VEE. The noninverting input (CLK) and SCLK are biased with a 45k pullup to VCC and a 30k pulldown to VEE. The single-ended inputs (SEL, EN) are each biased with a 30k pulldown to VEE and a 30k pullup to VCC.
Controlled-Impedance Traces
Input and output trace characteristics affect the performance of the MAX9316A. Connect input and output signals with 50 characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces.
Differential Clock Input Limits
The maximum magnitude of the differential signal applied to the differential clock input is 3.0V. This limit also applies to the difference between any reference voltage input and a single-ended input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously.
Output Termination
Terminate outputs with 50 to V CC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0.
Single-Ended Clock Input and VBB The differential clock input can be configured to accept a single-ended input. This is accomplished by connecting the on-chip reference voltage, VBB, to the inverting or noninverting input of the differential input as a reference. For example, the differential CLK, CLK input is converted to a noninverting, single-ended input by connecting VBB to CLK and connecting the single-ended input signal to CLK. Similarly, an inverting configuration is obtained by connecting VBB to CLK and connecting the single-ended input to CLK. With a differential input configured as single ended (using VBB), the singleended input can be driven to VCC and VEE or with a single-ended (LV)PECL/(LV)ECL signal. Note that the single-ended input must be least VBB 95mV or a differential input of at least 95mV to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table.
When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, leave it open. The V BB reference can source or sink 0.5mA. Use VBB only for an input that is on the same device as the VBB reference.
Chip Information
TRANSISTOR COUNT: 616 PROCESS: Bipolar
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7
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
CLK CLK VIH VBB VIL (CLK IS CONNECTED TO VBB)
Q_ VOH - VOL Q_
VOH
VOL
Figure 1. MAX9316A Switching Characteristics with Single-Ended Input
CLK VIHD - VILD CLK
VIHD
VILD
tPLHD1
tPHLD1
Q_ VOH - VOL Q_
VOH
VOL
80% 0V (DIFFERENTIAL) 20% Q_ - Q_ tR
80% 0V (DIFFERENTIAL) 20%
tF
Figure 2. MAX9316A Timing Diagram
8
_______________________________________________________________________________________
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
VIHD
SCLK
VILD
tPLHD3
tPHLD3
Q_ VOH - VOL Q_
VOH
VOL
80% 0V (DIFFERENTIAL) 20% Q_ - Q_ tR
80% 0V (DIFFERENTIAL) 20%
tF
Figure 3. MAX9316A Timing Diagram for SCLK
EN tS CLK SCLK OR CLK tPLHD Q_ Q_ OUTPUTS ARE LOW OUTPUTS STAY LOW tH tS
Figure 4. MAX9316A EN Timing Diagram
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9
1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver MAX9316A
Functional Diagram
VCC
VCC
Q0
45k CLK
45k
Q0
Q1 CLK Q1 30k 45k Q2 0 Q2
VEE
VEE
VCC
1
Q3
45k SCLK VCC VCC VEE SEL EN VBB 30k 30k D 30k VEE
Q3
Q4
30k
Q4
Q
30k VEE VCC
MAX9316A
10
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1:5 Differential (LV)PECL/(LV)ECL/ HSTL Clock and Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9316A
INCHES
N
MILLIMETERS MIN 2.35 0.10 0.35 0.23 MAX 2.65 0.30 0.49 0.32
E
H
DIM A A1 B C e E H L
MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.050 0.299 0.291 0.394 0.419 0.050 0.016
1.27 7.40 7.60 10.00 10.65 0.40 1.27
VARIATIONS:
1
INCHES
MILLIMETERS MIN 10.10 11.35 12.60 15.20 17.70 MAX 10.50 11.75 13.00 15.60 18.10 N MS013 16 AA 18 AB 20 AC 24 AD 28 AE
TOP VIEW
D
DIM D D D D D
MIN 0.398 0.447 0.496 0.598 0.697
MAX 0.413 0.463 0.512 0.614 0.713
A e B
C 0 -8 L
A1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .300" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0042
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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